Designing a new ternary arithmetic unit with overflow detection using reversible ternary gates

in this paper for the first time, a novel technique for designing signed reversible ternary parallel arithmetic circuit with an overflow detection capability to calculate six mathematical operations of A+B, A-B, A+1, A-1, A+B+1 and A-B-1 on two 2-trit signed ternary numbers on the basis of 1-input shift gates and 2-input MS gates which can be physically implemented in ion-trap technology in quantum computer was proposed. The presented circuit used the new proposed reversible ternary parallel adder with the quantum cost of 23 which had lower-cost in comparison with existing counterparts. Accordingly, the provided signed arithmetic circuit was optimized in terms of Quantum cost, the number of primitive gates, constant inputs and garbage outputs as much as possible. Inputs and outputs in this circuit were represented in the 3's complement system between -4 and +4. Also, in this paper, another computational circuit using the proposed parallel adder for performing six mathematical operations of A + B, A-B, A + 1, A-1, A + B + 1 and A-B-1 on two 2-trit unsigned ternary numbers was proposed. In this circuit, using the correction circuit, the calculation result was the same as the inputs in the unsigned ternary representation between 0 and 8.

Added to the advantages of the ternary logic application as opposed to binary logic, such as reducing the complexity of interconnects, and consistent with its application within the quantum computer and other technologies associated with the nanotechnology domain, reversible ternary circuit design is now being taken into consideration. This study sought to propose a new reversible 2-trit ternary parallel adder with a quantum cost of 23 and one constant input. When compared with the existing counterparts, the proposed circuit has lower quantum cost and constant inputs. Subsequently, the reversible ternary arithmetic circuit for six mathematical operations calculation of A+B, A-B, A+1, A-1, A+B+1 and A-B-1 for two 2-trit unsigned ternary numbers was proposed. In the proposed unsigned arithmetic circuit, two input numbers and the obtained results were coded in unsigned ternary representation ranging from 0 to 8. Next, the reversible ternary arithmetic circuit for two 2-trit signed ternary numbers with the quantum cost of 32 and one constant input was proposed. The proposed signed arithmetic circuit, similar to the proposed unsigned arithmetic, can be used to calculate six mathematical operations of A+B, A-B, A+1, A-1, A+B+1 and A-B-1; and in comparison with existing counterparts, it had lower quantum cost and constant inputs. In the proposed signed arithmetic circuit, two input numbers and the obtained results were in 3's complement representation ranging from -4 to +4. What follows is an introduced new module for detecting the overflow occurrence for signed numbers adding and subtracting calculations, and by adding it to the proposed reversible signed ternary arithmetic circuit, the overflow detection capability was provided for this circuit. All the proposed circuits were implemented using 1-qutrit shift gates and 2-qutrit MS gates which are primitive ternary gates in quantum computers and can be implemented in ion-trap technology.

Quantum ComputersReversible Ternary LogicParallel Adder and Reversible Arithmetic Unit